A novel ADPLL design using successive approximation frequency control

This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight reference cycles. ASICs in CMOS AMS 0:35mm and UMC 0:13mm have been manufactured and tested. Measurements show competitive results to state-of-the-art mixed-signal implementations. & 2008 Elsevier Ltd. All rights reserved.